`timescale 1ns/1ps
`default_nettype none

module frame_rate_controller (
    input  wire         I_sclk,
    input  wire         I_rst_n,
    input  wire         I_wrreq,
    output wire [1:0]   O_wrsel,
    input  wire         I_rdreq,
    output wire [1:0]   O_rdsel
);
//------------------------Parameter----------------------

//------------------------Local signal-------------------
reg  wrsel;
reg  rdsel;
reg  valid;

//------------------------Instantiation------------------

//------------------------Body---------------------------
//assign O_wrsel = wrsel[0]? 2'd0
//               : wrsel[1]? 2'd1
//               : 2'd2;
//assign O_rdsel = rdsel[0]? 2'd0
//              : rdsel[1]? 2'd1
//               : 2'd2;
assign O_wrsel =wrsel? 2'd1:2'd2;
assign O_rdsel =rdsel? 2'd1:2'd2;

// wrsel
always @(posedge I_sclk or negedge I_rst_n) begin
    if (~I_rst_n)
        wrsel <= 1'b1;
    else if (I_wrreq)
        wrsel <= ~wrsel;
end

// rdsel
always @(posedge I_sclk or negedge I_rst_n) begin
    if (~I_rst_n)
        rdsel <= 1'b0;
    else if (I_rdreq) begin
        if (I_wrreq)
            rdsel <= wrsel;
        else 
            rdsel <= valid;
    end
end

// valid
always @(posedge I_sclk or negedge I_rst_n) begin
    if (~I_rst_n)
        valid <= 1'b0;
    else if (I_wrreq)
        valid <= wrsel;
end

endmodule

`default_nettype wire

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